//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
//
//
// (C) Copyright 2006 Marvell International Ltd.
// All Rights Reserved
//
//------------------------------------------------------------------------------
//
//  Header:  monahans_intr.h
//
//  Defines the interrupt controller register layout and associated interrupt
//  sources and bit masks.
//
#ifndef __MONAHANS_INTR_H
#define __MONAHANS_INTR_H

#if __cplusplus
extern "C" {
#endif

#include <xllp_intc.h>

//-----------------------------------------------------
//
//  Define: IRQ_XXX
//
//  Interrupt sources numbers
//

// Following definition will be replaced by XLLP definition gradually
#define IRQ_USB2         46

#define IRQ_MVED       54
#define IRQ_MVED_DMA   48
#define IRQ_NAND         45
#define IRQ_QCI		   33
#define IRQ_RTCALARM   31
#define IRQ_RTC_TIC    30
#define IRQ_OSMR3      29
#define IRQ_OSMR2      28
#define IRQ_OSMR1      27
#define IRQ_OSMR0      26
#define IRQ_DMAC       25
#define IRQ_SSP        24
#define IRQ_MMC        23
#define IRQ_FFUART     22
#define IRQ_BTUART     21
#define IRQ_STUART     20
#define IRQ_ICP        19
#define IRQ_I2C        18
#define IRQ_LCD        17
#define IRQ_SSP2       16
#define IRQ_USIM       15
#define IRQ_AC97       14
#define IRQ_SSP4       13
#define IRQ_PMU        12
#define IRQ_USBFN      11
#define IRQ_GPIOXX_2   10
#define IRQ_GPIO1      9
#define IRQ_GPIO0      8
#define IRQ_OSMRXX_4   7
#define IRQ_PWRI2C     6
#define IRQ_MEMSTICK   5
#define IRQ_KEYPAD     4
#define IRQ_USBOHCI    3
#define IRQ_USBNONOHCI 2
#define IRQ_BASEBAND   1
#define IRQ_SSP3       0

// Max IRQ number would be 255, limited by WinCE's NKCallIntChain().
#define IRQ_GPIO_SHARE_BASE		(XLLP_INTC_S_MAX_ID+1) // Should be 53
#define IRQ_GPIO_SHARE(x)		(IRQ_GPIO_SHARE_BASE+x-2)
#define IRQ_TO_GPIO_NUM(x)      (x+2-IRQ_GPIO_SHARE_BASE)
#define NUM_OF_IRQ_GPIO_SHARE	(128-2) //GPIO0 and GPIO1 are not shared.
#define IRQ_GPIO_SHARE_MAX	    (IRQ_GPIO_SHARE_BASE+NUM_OF_IRQ_GPIO_SHARE-1)

//keep the same as the definition of XLLP_GPIO_AC97_INT_N in xllp_gpio_plat.h
#define IRQ_GPIO_AC97_INT_N 15


//------------------------------------------------------------------------------
//
//  Type: PXA_INTR_REG    
//
//  Interrupt control registers.
//

typedef XLLP_INTC_T  PXA_INTR_REG;
typedef XLLP_INTC_T *PPXA_INTR_REG;

typedef enum
{
	GPIO_MASK = 0,
	GPIO_RISE = 1,
	GPIO_FALL = 2,
	GPIO_BOTH = 3
};

#if __cplusplus
}
#endif

#endif 
